With the trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes, local interconnection has become of prime importance in semiconductor manufacturing. Local interconnects have been used to achieve increased packing density in sub-micron integrated circuit designs. Local interconnects are an extra level of interconnect used for connecting closely spaced elements in a layout design.
Local interconnects typically do not cross over any portion of other interconnect layers, although they may cross over field oxide regions. Local interconnects may be used to connect N+ regions to P+ regions or to connect source/drain regions to gates. Local interconnects must meet certain basic requirements to achieve the objective of increased packing density. The materials used for the local interconnects must provide for low contact resistance to source/drain regions and provide low sheet resistance. In order to prevent subsequent severe topography, local interconnects must be thin, e.g., less than 2500 Angstroms. Further, local interconnects must be capable of acting as a barrier to prevent interdiffusion of dopants between P and N regions.
Numerous techniques have been used to implement local interconnects. These techniques typically introduce new processing technologies above and beyond those used for the remainder of the device fabrication process flow. Such techniques include, for example, the use of titanium nitride for the local interconnect. Titanium is deposited and followed by a thermal treatment. However, this technique creates high sheet resistance and discontinuity over source/drain regions due to the thinning of the titanium nitride layer. An additional layer of titanium nitride may be formed by depositing titanium followed again by a thermal treatment to overcome these problems but the process steps then become complicated.
Another technique includes the use of a polycide layer for the local interconnect. Selective deposition of refractory metals on silicon has also been proposed for local interconnects. The quality of the conducting element formed using such techniques varies, with some techniques resulting in fairly good conductors. Such techniques, however, typically introduce additional process complexity to the normal process flow. This additional complexity tends to decrease device yield and increase cost.
It is desirable to use local interconnection in integrated circuit design because of the layout area savings. It would be desirable to provide a local interconnection fabrication technique which does not introduce additional process complexities.